TI-84 Plus CE confirmed ez80!

[chickendude]

It appears critor got their hands on an 83 Premium CE (what appears to be the French version of the 84PCE), and confirmed that the processor is indeed an ez80! You can read more about it here:
http://tiplanet.org/forum/viewtopic.php?p=175931#07

I think this is great news, this is looking to be the device i've wanted to program ever since i was in middle school. The ez80 even at the same clock frequency as the z80 would still be several times (or more) faster due to pipelining and other things i don't really understand. I believe the registers (bc, de, hl, ix, iy, sp, etc.) are also 24-bit.

Here's the ez80 user manual for anyone interested:
http://www.zilog.com/docs/um0077.pdf

What are your thoughts? It's scheduled to come out in Spring of this year, can't wait to get my hands on one of these!

[NanoWar]

Just wow.

Registers are still 16 bit but the MBASE register (+8 bytes) is prefixed and functions as a page memory pointer to max of 16MB .

In Z80 mode, the BC, DE, and HL register pairs and the IX and IY registers function as 16-bit registers for multibyte operations and indirect addressing. The active Stack Pointer is the 16-bit Stack Pointer Short register (SPS). The Program Counter register (PC) is also 16 bits long. The address is 24 bits long and is composed as {MBASE, ADDR[15:0]}. While the MBASE register is only used during Z80 mode operations, it cannot be written while operating in this mode. Tables 1 and 2 lists the CPU registers and bit flags during Z80 mode operation.

Also the pipelining is very useful and can speed everything up. Max would be 3x, but when there is a jump, the next instruction cannot be read before the next pc is not determined.

The CPU pipeline reduces the overall cycle time for each instruction. In principle, each instruction must be fetched, decoded, and executed. This process normally spans at least three cycles. The CPU pipeline, however, can reduce the overall time of some instructions to as little as one cycle by allowing the next instruction to be prefetched and decoded while it executes the current instruction as displayed in Figure 2. The CPU operates on multiple instructions simultaneously to improve operating efficiency.

[chickendude]

Registers are 16-bit in z80 mode, in ez80 mode they are 24-bit, but there's no way to directly access the upper 8 bits without shift instructions (eg. add hl,hl \ rla *8). But you can load immediate values into them, ld hl,$FFFFFF and perform 24-bit addition/subtraction. There's also a MLT instruction! (Though it's only works with 8-bit registers: hl=h*l, bc=b*c, de=d*e).

I've been reading about the pipeline and have a basic idea how it works, but i didn't really understand all the examples. A write cycle basically pauses the pipeline? Is there anywhere i can read more on how the pipeline works?

[NanoWar]

http://en.wikipedia.org/wiki/Instruction_pipeline

Oh cool, didn't read enough about the 24bit thing. MUL is awesome!

[chickendude]

Thanks, i'll read through that and see if things make a bit more sense. I really hope that the LCD won't be a bottle neck anymore and that fullscreen smoothscrolling games will be a possibility now!

[NanoWar]

Usually the z80 can process one instruction at a time. It has to be fetched, decoded (maybe fetch more bytes as the 0 in ld a, 0), executed and then there is a write back cycle where the result is stored in the register. The pipelining parallelizes this like this (upper picture is WITH pipelining, bottom is without)

(I know you can understand some german )

[chickendude]

Yeah, i know the basics behind how fetching decoding and all of that works, i also understand the principle behind pipelining, but what i couldn't quite understand is why sometimes you get "bubbles". The manual briefly mentions this and talks about it in one of the diagrams, but it's still not exactly clear to me what causes them.

EDIT: I also wonder if SMC might pose potential problems for a pipelined processor. Probably not in the traditional SMC sense of overwriting a ld value:

Code: Select all

    ld hl,smc
    ld (hl),11
smc = $+1
    ld a,10

..since the fetch cycle will just be fetching the opcode not the immediate value, but what about if you're changing the opcode? For example, changing an OR to an XOR? I imagine it wouldn't register the change since the opcode has already been fetched. I can't think of any situation where it'd be a real issue, though.

[NanoWar]

Yes that's true, it might automatically flush the pipeline. If it doesn't you would need some instructions in between smc writing and the target.

[chickendude]

calc84 just added ez80 support to spasm!
https://github.com/alberthdev/spasm-ng

(more info here)

EDIT: Just built for Linux and it compiles fine (just run make) I dunno what dependencies it needs, probably whatever spasm needs, but i've already installed all that before so i couldn't tell you what it all is.

[NanoWar]

Wow, that is amazing. I was also planning on adding features to SPASM (I already have) and upload it to github!

Whooosh!
Awesome!
Also, building Spasm-ng was way easier than it used to be with original spasm.
I'm looking forward for the new TI